This invention generally relates to semiconductor processing methods for forming salicides (self-aligned suicides) over silicon areas and more particularly to a method for forming cobalt salicides for deep-submicron ( less than 0.25 micron) and nanometer ( less than 0.1 micron) MOSFET semiconductor devices to reduce parasitic current leakage including junction leakage.
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Contact resistances between functioning areas of a MOSFET device such as a source or drain regions and polysilicon electrodes are critical to the functioning of a MOSFET device, for example a CMOS transistor. For example, metal interconnect features are formed to connect source/drain and gate electrode regions to other parts of a functioning semiconductor device. Source and drain regions of a transistor are doped portions of a semiconductor substrate, for example single crystal silicon or epitaxially grown silicon. The source and drain regions are typically formed by implanting ions in the silicon substrate to achieve n-doped regions or p-doped regions. To prevent the contamination of the silicon substrate by contacting metal interconnects and to reduce a sheet resistance of the polysilicon gate electrode, an intermediate layer of a metal silicide is formed over the source/drain and gate electrode contact regions, for example, titanium silicide or cobalt silicide. Metal silicides are thermally stable at higher temperatures and prevent metals from diffusing into the silicon substrate as well as reduce a sheet resistance between the contact regions, for example the source/drain regions and the channel edge.
To satisfy the requirements for low-resistance for the gate and source/drain contact regions cobalt silicide (e.g., CoSi2) and titanium silicide (TiSi2) have been the most commonly used suicides to form salicides. The severity of the effect of increased resistance on the drain side of the transistor depends on whether the transistor is operating in the saturated region or the linear region, the reduction of drain voltage having less effect if operation is in the saturated region. Increased contact resistance on the source side of the transistor is more severe, reducing the effective gate voltage, and severely degrading device performance. It has been found that self aligned silicides (salicides) covering the entire source/drain area is the one of the most effective solutions to decreasing contact and sheet resistance and improving device performance allowing device scaling below 0.25 microns. A low sheet and contact resistance at the source and drain regions as well as the polysilicon gate is critical to high speed digital CMOS technology and RF applications.
One problem in forming salicides is that the sheet resistance of TiSi2 increases with decreasing design rules or gate length of the polysilicon gate. TiSi2 tends to agglomerate with increased sheet resistance when formed overlying narrow contact regions and subjected to high annealing temperatures, for example, using a rapid thermal anneal (RTA). Consequently, CoSi2 is a preferred material for forming salicides for sub-quarter micron and particularly, sub 0.1 micron (nanometer) devices since the sheet resistance of CoSi2 is independent of the size of the contact region. For example, the required phase transformation to form the low electrical resistance crystalline phase takes place at lower temperatures from about 600xc2x0 C. to about 700xc2x0 C. without the coincident problem of silicide agglomeration.
In a typical salicide process, a metal, for example titanium or cobalt is deposited to cover the gate, source and drain regions. The metal is then subjected to a two step high temperature anneal where a metal silicide is formed by binary diffusion of silicon and metal atoms thereby forming metal silicides. Carrying out the annealing process in nitrogen causes formation of metal nitrides within the metal, slowing the silicon diffusion to prevent what is referred to as bridging, where silicon diffuses into the sidewall regions of the deposited metal along the gate or sidewall spacers causing a short electrical circuit between the gate electrode and the source/drain region. The likelihood of bridging increases as the annealing temperature is increased, providing another factor favoring the use of cobalt silicide.
COSi2 salicides however, have been found to have serious drawbacks and limitations as well, especially as design rules decrease to 0.1 micron and below. For example CoSi2 salicides have been found to have sporadically high parasitic current leakage paths including junction and diode leakage. One factor contributing to increased junction leakage in the use of CoSi2 is the roughness of the interface at the COSi2/silicon interface caused by CoSi2 xe2x80x9cspikingxe2x80x9d where Co diffuses unevenly into the silicon substrate. Various approaches proposed to improve this problem including various low and high temperature annealing treatments have met with limited success.
There is therefore a need in the semiconductor processing art to develop a method for forming improved CoSi2 salicides having reduced parasitic electrical leakage paths while maintaining a low sheet resistance.
It is therefore an object of the invention to provide a method for forming improved CoSi2 salicides having reduced parasitic electrical leakage paths while maintaining a low sheet resistance thereby improving electrical behavior while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming salicides with reduced junction leakage.
In a first embodiment, the method includes providing a semiconductor process wafer comprising a silicon substrate; inducing amorphization within the silicon substrate to a form a first amorphous region having a first predetermined depth measured from the silicon substrate surface; carrying out at least one first thermal annealing process to controllably partially recrystallize the first amorphous region to produce a second amorphous region having a second predetermined depth less than the first predetermined depth; depositing a metal layer over selected areas of the silicon substrate comprising the second amorphous region; and, carrying out at least one second thermal annealing process to form a metal silicide.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.